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gs840z18/36at-180/166/150/100 4mb pipelined and flow through synchronous nbt srams 180 mhz?100 mhz 3.3 v v dd 2.5 v and 3.3 v v ddq 100-pin tqfp commercial temp industrial temp rev: 1.05 2/2009 1/23 ? 2001, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? 256k x 18 and 128k x 36 configurations ? user configurable pipeline and flow through mode ? nbt (no bus turn around) functionality allows zero wait read-write-read bus utilization ? fully pin compatible with both pipelined and flow through ntram?, nobl? and zbt? srams ? pin-compatible with 2m, 8m and 16m devices ? 3.3 v +10%/?5% core power supply ? 2.5 v or 3.3 v i/o supply ? lbo pin for linear or interleave burst mode ? byte write operation (9-bit bytes) ? 3 chip enable signals for easy depth expansion ? clock control, registered address, data, and control ? zz pin for automatic power-down ? jedec-standard 100- lead tqfp package ? rohs-compliant 100-lead tqfp package available functional description the gs840z18/36at is a 4mbit synchronous static sram. gsi's nbt srams, like zbt, ntram, nobl or other pipelined read/double late write or flow through read/single late write srams, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched fr om read to write cycles. because it is a synchronous devi ce, address, data inputs, and read/ write control inputs are ca ptured on the rising edge of the input clock. burst order control ( lbo ) must be tied to a power rail for proper operation. asynchronous inputs include the sleep mode enable (zz) and outp ut enable. output enable can be used to override the synchronous control of the output drivers and turn the ram's out put drivers off at any time. write cycles are internally self- timed and initiated by the rising edge of the clock input. this feature eliminates complex off- chip write pulse generation required by asynchronous srams and simplifies input signal timing. the gs840z18/36at may be configured by the user to operate in pipeline or flow through mode. operating as a pipelined synchronous device, in addition to the rising-edge- triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. for read cycles, pipelined sram output data is temporarily stored by the edge triggered output regi ster during the access cycle and then released to the output driv ers at the next rising edge of clock. the gs840z18/36at is implemented with gsi's high performance cmos technology and is available in a jedec- standard 100-pin tqfp package. parameter synopsis ?180 ?166 ?150 ?100 pipeline 3-1-1-1 tcycle t kq i dd 5.5 ns 3.2 ns 335 ma 6.0 ns 3.5 ns 310 ma 6.6 ns 3.8 ns 280 ma 10 ns 4.5 ns 190 ma flow through 2-1-1-1 t kq tcycle i dd 8 ns 9.1 ns 210 ma 8.5 ns 10 ns 190 ma 10 ns 12 ns 165 ma 12 ns 15 ns 135 ma
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 2/23 ? 2001, gsi technology gs840z18at pinout (package t) note: pins marked with nc can be tied to either vdd or vss. these pins can also be left floating. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq b dq b v ss v ddq dq b dq b ft v dd nc v ss dq b dq b v ddq v ss dq b dq b dqp b v ss v ddq v ddq v ss dq a dq a v ss v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ss dq a dq a v ss v ddq lbo a a a a a 1 a 0 nc nc v ss v dd nc nc a a a a a a a a e 1 e 2 nc nc b b b a e 3 ck w cke v dd v ss g adv nc nc a a a 256k x 18 top view dqp a a nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 3/23 ? 2001, gsi technology gs840z36at pinout (package t) note: pins marked with nc can be tied to either v dd or v ss . these pins can also be left floating. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c dq c v ss v ddq dq c dq c ft v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d v ss v ddq v ddq v ss dq b dq b v ss v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ss dq a dq a v ss v ddq lbo a a a a a 1 a 0 nc nc v ss v dd nc nc a a a a a a a a e 1 e 2 b d b c b b b a e 3 ck w cke v dd v ss g adv nc nc a a a 128k x 36 top view dq b dqp b dq b dq b dq b dq a dq a dq a dq a dqp a dq c dq c dq c dq d dq d dq d dqp d dq c dqp c 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 4/23 ? 2001, gsi technology 100-pin tqfp pin descriptions symbol type description a 0 , a 1 in burst address inputs; preload the burst counter a in address inputs ck in clock input signal b a in byte write signal for data inputs dq a1 -dq a9 ; active low b b in byte write signal for data inputs dq b1 -dq b9 ; active low b c in byte write signal for data inputs dq c1 -dq c9 ; active low b d in byte write signal for data inputs dq d1 -dq d9 ; active low w in write enable; active low e 1 in chip enable; active low e 2 in chip enable; active high; for self decoded depth expansion e 3 in chip enable; active low, for self decoded depth expansion g in output enable; active low adv in advance / load ?burst address counter control pin cke in clock input buffer enable; active low dq a i/o byte a data input and output pins dq b i/o byte b data input and output pins dq c i/o byte c data input and output pins dq d i/o byte d data input and output pins zz in power down control; active high ft in pipeline/flow through mode control; active low lbo in linear burst order; active low v dd in 3.3 v power supply v ss in ground v ddq in 3.3 v output power supply for noise reduction nc ? no connect
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 5/23 ? 2001, gsi technology gs840z18/36a nbt sram f unctional block diagram k sa1 sa0 burst counter lbo adv memory array g ck cke d q ft dqa?dqn k sa1? sa0? d q match write address register 2 write address register 1 write data register 2 write data register 1 k k k k k k sense amps write drivers read, write and data coherency control logic ft a0? e 3 e 2 e 1 w b d b c b b b a
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 6/23 ? 2001, gsi technology functional details clocking deassertion of the clock enable ( cke ) input blocks the clock input fr om reaching the ram's internal circuits. it may be used to suspend ram operations. failure to observ e clock enable set-up or hold requirem ents will result in erratic operation. pipelined mode read and write operations all inputs (with the exception of output enab le, linear burst order and sleep) are synchr onized to rising clock edges. single c ycle read and write operat ions must be initiated with the advance/ load pin (adv) held low, in order to load the new address. device activation is accomplished by asserting al l three of the chip enable inputs ( e 1 , e 2, and e 3 ). deassertion of any one of the enable inputs will deactivate the device. read operation is initiated when the following conditions are satisfied at the rising edge of clock: cke is asserted low, all three chip enables ( e1 , e2, and e3 ) are active, the write enable input signal w is deasserted high, and adv is asserted low. the address presented to the address inputs is latched in to address register and presented to the memory core and control logic. the contr ol logic determines that a read access is in progress and allows th e requested data to propagate to the input of the output regist er. at the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. write operation occurs when the ram is select ed, cke is active and the write input is sa mpled low at the rising edge of clock. the byte write enable inputs ( b a , b b , b c, and b d ) determine which bytes will be written. all or none may be activated. a write cycle with no byte write inputs active is a no-op cycle. the pipeline d nbt sram provides double late write functionality, matching th e write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). at the first r ising edge of clock, enable, write, byte write(s) , and address are registered. the data in a ssociated with that address is required a t the third rising edge of clock. flow through mode read and write operations operation of the ram in flow through mode is very similar to operations in pipeline mode. activation of a read cycle and the us e of the burst address counter is identical. in flow through mode the device may begin driving out new data immediately after new address are clocked into the ram, rather than holding new data until the following (second) clock edge. therefore, in flow through mode the read pipeline is one cycle shorter than in pipeline mode. write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, pre serving the ability to turn the bus from reads to writes without inserting any dead cycles. while the pipelined nbt rams implement a double late write protocol, in flow through mode a single late wr ite protocol mode is observed. therefore, in flow through mode , address and control are registered on the first rising edge of cl ock and data in is required at the data input pins at the seco nd rising edge of clock. function w b a b b b c b d read h x x x x write byte ?a? l l h h h write byte ?b? l h l h h write byte ?c? l h h l h write byte ?d? l h h h l write all bytes l l l l l write abort/nop l h h h h
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 7/23 ? 2001, gsi technology synchronous truth table operation type address ck cke adv w bx e 1 e 2 e 3 g zz dq notes read cycle, begin burst r external l-h l l h x l h l l l q read cycle, continue burst b next l-h l h x x x x x l l q 1,10 nop/read, begin burst r external l-h l l h x l h l h l high-z 2 dummy read, continue burst b next l-h l h x x x x x h l high-z 1,2,10 write cycle, begin burst w external l-h l l l l l h l x l d 3 write abort, begin burst d none l-h l l l h l h l x l high-z 1 write cycle, continue burst b next l-h l h x l x x x x l d 1,3,10 write abort, continue burst b next l-h l h x h x x x x l high-z 1,2,3,10 deselect cycle, power down d none l-h l l x x h x x x l high-z deselect cycle, power down d none l-h l l x x x x h x l high-z deselect cycle, power down d none l-h l l x x x l x x l high-z deselect cycle, continue d none l-h l h x x x x x x l high-z 1 sleep mode none x x x x x x x x x h high-z clock edge ignore, stall current l-h h x x x x x x x l - 4 notes: 1. continue burst cycles, whether read or wr ite, use the same control inputs. a deselect continue cycle can only be entered into if a dese - lect cycle is executed first. 2. dummy read and write abort can be considered nops because the sram performs no operation. a write abort occurs when the w pin is sampled low but no byte write pins are active so no writ e operation is performed. 3. g can be wired low to minimize the number of control signals provi ded to the sram. output drivers will automatically turn off du ring write cycles. 4. if cke high occurs during a pipelined read cycle, the dq bus will remain active (low z). if cke high occurs during a write cycle, the bus will remain in high z. 5. x = don?t care; h = logic high; l = logic low; bx = high = all byte write signals are high; bx = low = one or more byte/write signals are low 6. all inputs, except g and zz must meet setup and hold times of rising clock edge. 7. wait states can be inserted by setting cke high. 8. this device contains circuitry that ensur es all outputs are in high z during power-up. 9. a 2-bit burst counter is incorporated. 10. the address counter is incriminat ed for all burst continue cycles.
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 8/23 ? 2001, gsi technology pipelined and flow through r ead-write control state diagram deselect new read new write burst read burst write w r b r b w d d b b w r d b w r d d current state (n) next state (n+1) transition ? input command code key notes 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b, and d represent input command codes as indicated in t he synchronous truth table. clock (ck) command current state next state ? n n+1 n+2 n+3 ??? current state and next state definition for pipelined and flow through read /write control state diagram w r
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 9/23 ? 2001, gsi technology pipeline mode da ta i/o state diagram intermediate intermediate intermediate intermediate intermediate intermediate high z (data in) data out (q valid) high z b w b r b d r w r w d d current state (n) next state (n+2) transition ? input command code key transition intermediate state (n+1) notes 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b, and d represent input command codes as indicated in the truth tables. clock (ck) command current state intermediate ? n n+1 n+2 n+3 ??? current state and next state definition for pipeline mode data i/o state diagram next state state
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 10/23 ? 2001, gsi technology flow through mode da ta i/o state diagram high z (data in) data out (q valid) high z b w b r b d r w r w d d current state (n) next state (n+1) transition ? input command code key notes 1. the hold command (cke low) is not shown because it prevents any state change. 2. w, r, b, and d represent input command codes as indicated in the truth tables. clock (ck) command current state next state ? n n+1 n+2 n+3 ??? current state and next state definition for: pipelined and flow through read write control state diagram
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 11/23 ? 2001, gsi technology burst cycles although nbt rams are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back read s or writes may also be performed. nb t srams provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementatio ns. the adv control pin, when driven high, commands the sram to advance the internal address counter and use the c ounter generated address to read or write the sram. the starting address for the first cy cle in a burst cycle series is loaded into the sram by driving the adv pin low, into load mode. burst order the burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. the burst sequence is determined by the state of the linear burst order pin ( lbo ). when this pin is low, a linear burst sequence is selected. when the ram is installed with the lbo pi n tied high, interleaved burst sequence is selected. see the tab les below for details. note: there is a pull-down device on the zz pin, so this input pin can be unconnected and the chip will operate in the default sta tes as specified in the above tables. burst counter sequences bpr 1999.05.18 mode pin functions mode name pin name state function burst order control lbo l linear burst h interleaved burst power down control zz l or nc active h standby, i dd = i sb note: the burst counter wraps to initial state on the 5th clock. note: the burst counter wraps to initial state on the 5th clock. linear burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 interleaved burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 12/23 ? 2001, gsi technology sleep mode during normal operation, zz must be pulled low, either by the us er or by its internal pull-down resistor. when zz is pulled hig h, the sram will enter a power sleep mode after 2 cycles. at this time, internal stat e of the sram is preserved. when zz returns t o low, the sram operates normally after 2 cycles of wake up time. sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to i sb 2. the duration of sleep mode is dictated by the length of tim e the zz is in a high state. after ente ring sleep mode, all inputs except zz become disabled and all outputs go to high-z the zz pin is an async hronous, active high input that cau ses the device to enter sleep mo de. when the zz pin is driven high, i sb 2 is guaranteed after the time tzzi is met. because zz is an asynchronous input, pending operations or operations in progress may not be properly completed if zz is asserted. therefore, sleep mode must not be initiat ed until valid pending operations are completed. similarly, when exitin g sleep mode during tzzr, only a deselect or read commands may be applied while the sram is recovering from sleep mode. sleep mode timing diagram designing for compatibility the gsi nbt srams offer users a configurable selection between flow through mode and pipeline mode via the ft signal found on pin 14. not all vendors offer this option, however, most mark pin 14 as v dd or v ddq on pipelined parts and v ss on flow through parts. gsi nbt srams are fully compatible with these sockets. pin 66, a no connect (nc) on gsi?s gs840z18/36a nbt sram, th e parity error open drain output on gsi?s gs881z18/36 nbt sram, is often marked as a power pin on other vendor?s nbt-compatible srams. speci fically, it is marked v dd or v ddq on pipelined parts and v ss on flow through parts. users of gsi nbt devices who are not actually using th e bytesafe? parity feature may want to design the board site for the ram with pin 66 tied high through a 1k ohm resistor in pipeline mode applications or tied low in flow through mode applications in order to keep the option to use non-configurable devices open. by using the pull- up resistor, rather than tying the pin to one of the power rail s, users interested in upgradi ng to gsi?s bytesafe nbt srams (gs881z18/36), featuring parity error det ection and jtag boundary scan, will be r eady for connection to the active low, open drain parity error output driver at pi n 66 on gsi?s tqfp bytesafe rams. tzzr tzzh tzzs tkl tkl tkh tkh tkc tkc ck zz
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 13/23 ? 2001, gsi technology note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the absolute maximum ra tings, for an extended period of time, may affect reliability of this component. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ? 0.5 to 4.6 v v ddq voltage in v ddq pins ? 0.5 to 4.6 v v i/o voltage on i/o pins ? 0.5 to v ddq +0.5 ( ? 4.6 v max.) v v in voltage on other input pins ? 0.5 to v dd +0.5 ( ? 4.6 v max.) v i in input current on any pin +/ ? 20 ma i out output current on any i/o pin +/ ? 20 ma p d package power dissipation 1.5 w t stg storage temperature ? 55 to 125 o c t bias temperature under bias ? 55 to 125 o c power supply voltage ranges parameter symbol min. typ. max. unit notes 3.3 v supply voltage v dd 3.0 3.3 3.6 v 3.3 v v ddq i/o supply voltage v ddq3 3.0 3.3 3.6 v 2.5 v v ddq i/o supply voltage v ddq2 2.3 2.5 2.7 v notes: 1. the part numbers of industrial temperatur e range versions end the character ?i?. un less otherwise noted, all performance spe cifica - tions quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc.
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 14/23 ? 2001, gsi technology logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 2.0 ? v dd + 0.3 v 1 v dd input low voltage v il ? 0.3 ? 0.8 v 1 v ddq3 i/o input high voltage v ihq3 2.0 ? v ddq + 0.3 v 1,3 v ddq3 i/o input low voltage v ilq3 ? 0.3 ? 0.8 v 1,3 v ddq2 i/o input high voltage v ihq2 0.6*v dd ? v ddq + 0.3 v 1,3 v ddq2 i/o input low voltage v ilq2 ? 0.3 ? 0.3*v dd v 1,3 notes: 1. the part numbers of industrial temperatur e range versions end the character ?i?. un less otherwise noted, all performance spe cifica - tions quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v. recommended operating temperatures parameter symbol min. typ. max. unit notes ambient temperature (com mercial range versions) t a 0 25 70 ? c 2 ambient temperature (industrial range versions) t a ? 40 25 85 ? c 2 notes: 1. the part numbers of industrial temperatur e range versions end the character ?i?. un less otherwise noted, all performance spe cifica - tions quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 50% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measure ment and timing 50% tkc v dd + 2.0 v 50% v dd v il
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 15/23 ? 2001, gsi technology note: these parameters are sample tested. capacitance (t a = 25 o c, f = 1 mh z , v dd = 2.5 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf input/output capacitance c i/o v out = 0 v 6 7 pf ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v ddq /2 output load fig. 1 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. device is deselected as defined by the truth table. dq v ddq/2 50 ? 30pf * output load 1 * distributed test jig capacitance
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 16/23 ? 2001, gsi technology dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ? 1 ua 1 ua zz input current i in1 v dd ? v in ? v ih 0 v ?? v in ?? v ih ? 1 ua ? 1 ua 1 ua 100 ua ft input current i in2 v dd ? v in ? v il 0 v ?? v in ?? v il ? 100 ua ? 1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ? 1 ua 1 ua output high voltage v oh2 i oh = ? 8 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh3 i oh = ? 8 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 8 ma ? 0.4 v operating currents parameter test conditions symbol - 180 - 166 - 150 - 100 unit 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c operating current device selected; all other inputs ? v ih o r ?? v il output open i dd pipeline 335 345 310 320 280 290 190 200 ma i dd flow-thru 210 220 190 200 165 175 135 145 ma standby current zz ?? v dd ? 0.2 v i sb pipeline 20 30 20 30 20 30 20 30 ma i sb flow-thru 20 30 20 30 20 30 20 30 ma deselect current device deselected; all other inputs ?? v ih or ? v il i dd pipeline 55 65 50 60 50 60 40 50 ma i dd flow-thru 40 50 40 50 35 45 35 45 ma
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 17/23 ? 2001, gsi technology ac electrical characteristics notes: 1. these parameters are sampled and are not 100% tested 2. zz is an asynchronous signal. however, in order to be recognized on any given clock cycl e, zz must meet the specified setup a nd hold times as specified above. parameter symbol -180 -166 -150 -100 unit min max min max min max min max pipeline clock cycle time tkc 5.5 ? 6.0 ? 6.7 ? 10 ? ns clock to output valid tkq ? 3.2 ? 3.5 ? 3.8 ? 4.5 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns flow through clock cycle time tkc 9.1 ? 10.0 ? 12.0 ? 15.0 ? ns clock to output valid tkq ? 8.0 ? 8.5 ? 10.0 ? 12.0 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock high time tkh 1.3 ? 1.3 ? 1.3 ? 1.3 ? ns clock low time tkl 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in high-z thz 1 1.5 3.2 1.5 3.5 1.5 3.8 1.5 5 ns g to output valid toe ? 3.2 ? 3.5 ? 3.8 ? 5 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 3.2 ? 3.5 ? 3.8 ? 5 ns setup time ts 1.5 ? 1.5 ? 1.5 ? 2.0 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? ns
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 18/23 ? 2001, gsi technology pipeline mode timing write a read b suspend read c write d write no-op read e deselect thz tkqx tkq tlz th ts th ts th ts th ts th ts th ts th ts th ts tkc tkc tkl tkl tkh tkh ab cd e d(a) d(d) q(e) q(b) q(c) ck a cke e * adv w bn dq
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 19/23 ? 2001, gsi technology flow through mode timing write a write b write b+1 read c cont read d write e read f write g d(a) d(b) d(b+1) q(c) q(d) d(e) q(f) d(g) tolz toe tohz tkqx tkq tlz thz tkqx tkq tlz th ts th ts th ts th ts th ts th ts th ts tkc tkc tkl tkl tkh tkh ab c defg *note: e = high(false) if e1 = 1 or e2 = 0 or e3 = 1 ck cke e adv w bn a0?an dq g
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 20/23 ? 2001, gsi technology tqfp package drawing (package t) bpr 1999.05.18 d1 d e1 e pin 1 b e c l l1 a2 a1 y ? notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion. symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 ? 0.20 d terminal dimension 21.9 22.0 22.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch ? 0.65 ? l foot length 0.45 0.60 0.75 l1 lead length ? 1.00 ? y coplanarity 0.10 ? lead angle 0 ? ? 7 ?
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 21/23 ? 2001, gsi technology ordering information?gsi nbt synchronous srams org part number 1 type package speed 2 (mhz/ns) t a 3 256k x 18 gs840z18at-180 nbt pipeline/flow through tqfp 180/8 c 256k x 18 gs840z18at-166 nbt pipeline/flow through tqfp 166/8.5 c 256k x 18 gs840z18at-150 nbt pipeline/flow through tqfp 150/10 c 256k x 18 gs840z18at-100 nbt pipeline/flow through tqfp 100/12 c 128k x 36 gs840z36at-180 nbt pipeline/flow through tqfp 180/8 c 128k x 36 gs840z36at-166 nbt pipeline/flow through tqfp 166/8.5 c 128k x 36 gs840z36at-150 nbt pipeline/flow through tqfp 150/10 c 128k x 36 gs840z36at-100 nbt pipeline/flow through tqfp 100/12 c 256k x 18 GS840Z18AT-180I nbt pipeline/flow through tqfp 180/8 i 256k x 18 gs840z18at-166i nbt pipeline/flow through tqfp 166/8.5 i 256k x 18 gs840z18at-150i nbt pipeline/flow through tqfp 150/10 i 256k x 18 gs840z18at-100i nbt pipeline/flow through tqfp 100/12 i 128k x 36 gs840z36at-180i nbt pipeline/flow through tqfp 180/8 i 128k x 36 gs840z36at-166i nbt pipeline/flow through tqfp 166/8.5 i 128k x 36 gs840z36at-150i nbt pipeline/flow through tqfp 150/10 i 128k x 36 gs840z36at-100i nbt pipeline/flow through tqfp 100/12 i 256k x 18 gs840z18agt-180 nbt pipeline/flow through rohs-compliant tqfp 180/8 c 256k x 18 gs840z18agt-166 nbt pipeline/flow through rohs-compliant tqfp 166/8.5 c 256k x 18 gs840z18agt-150 nbt pipeline/flow through rohs-compliant tqfp 150/10 c 256k x 18 gs840z18agt-100 nbt pipeline/flow through rohs-compliant tqfp 100/12 c 128k x 36 gs840z36agt-180 nbt pipeline/flow through rohs-compliant tqfp 180/8 c 128k x 36 gs840z36agt-166 nbt pipeline/flow through rohs-compliant tqfp 166/8.5 c notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs8z36a-10 0it. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipeline mode and the latency (ns) in flow through mod e. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, onl y some of which are covered in this data sheet. see the gsi technology web site ( www.gsitechnology.com ) for a complete listing of current offerings
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 22/23 ? 2001, gsi technology 128k x 36 gs840z36agt-150 nbt pipeline/flow through rohs-compliant tqfp 150/10 c 128k x 36 gs840z36agt-100 nbt pipeline/flow through rohs-compliant tqfp 100/12 c 256k x 18 gs840z18agt-180i nbt pipeline/flow through rohs-compliant tqfp 180/8 i 256k x 18 gs840z18agt-166i nbt pipeline/flow through rohs-compliant tqfp 166/8.5 i 256k x 18 gs840z18agt-150i nbt pipeline/flow through rohs-compliant tqfp 150/10 i 256k x 18 gs840z18agt-100i nbt pipeline/flow through rohs-compliant tqfp 100/12 i 128k x 36 gs840z36agt-180i nbt pipeline/flow through rohs-compliant tqfp 180/8 i 128k x 36 gs840z36agt-166i nbt pipeline/flow through rohs-compliant tqfp 166/8.5 i 128k x 36 gs840z36agt-150i nbt pipeline/flow through rohs-compliant tqfp 150/10 i 128k x 36 gs840z36agt-100i nbt pipeline/flow through rohs-compliant tqfp 100/12 i ordering information?gsi nbt synchronous srams org part number 1 type package speed 2 (mhz/ns) t a 3 notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs8z36a-10 0it. 2. the speed column indicates the cycle frequenc y (mhz) of the device in pipeline mode and the latency (ns) in flow through mod e. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, onl y some of which are covered in this data sheet. see the gsi technology web site (www.gsitechnology.com ) for a complete listing of current offerings
gs840z18/36at-180/166/150/100 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05 2/2009 23/23 ? 2001, gsi technology 4mb synchronous nbt dat asheet revision history ds/daterev. code: old; new types of changes format or content page /revisions/reason 840z18a_r1 ? creation of new datasheet 840z18a_r1; 840z18a_r1_01 content ? updated power numbers in table on page 1 and operating currents table 840z18a_r1_01; 840z18a_r1_02 content ? removed 200 mhz speed bin from entire document ? removed pin locations from pin description table 840z18a_r1_02; 840z18a_r1_03 format/content ? updated format ? updated timing diagrams ? added pb-free information for tqfp 840z18a_r1_03; 840z18a_r1_04 content ? removed 2.5 v info from power supply voltage range table (pg. 13) ? removed 2.5 v supply info from logic level table (pg. 14) ? changed pin 16 from vdd to nc and added note to pinouts (pg. 2, 3) 840z18a_r1_04; 840z18a_r1_05 content ? updated pinout (pg. 3)

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